SAM7X256_14 Datasheet, PDF (495/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 36-9. Disabling Low-power Mode
Bus Activity Detected
CAN BUS
LPM
(CAN_MR)
SLEEP
(CAN_SR)
WAKEUP
(CAN_SR)
Message lost
Message x
Interframe synchronization
MRDY
(CAN_MSRx)
36.7 Functional Description
36.7.1 CAN Controller Initialization
After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated by the Power
Management Controller (PMC) and the CAN controller interrupt line must be enabled by the interrupt controller (AIC).
The CAN controller must be initialized with the CAN network parameters. The CAN_BR register defines the sampling
point in the bit time period. CAN_BR must be set before the CAN controller is enabled by setting the CANEN field in the
CAN_MR register.
The CAN controller is enabled by setting the CANEN flag in the CAN_MR register. At this stage, the internal CAN
controller state machine is reset, error counters are reset to 0, error flags are reset to 0.
Once the CAN controller is enabled, bus synchronization is done automatically by scanning eleven recessive bits. The
WAKEUP bit in the CAN_SR register is automatically set to 1 when the CAN controller is synchronized (WAKEUP and
SLEEP are stuck at 0 after a reset).
The CAN controller can start listening to the network in Autobaud Mode. In this case, the error counters are locked and a
mailbox may be configured in Receive Mode. By scanning error flags, the CAN_BR register values synchronized with the
network. Once no error has been detected, the application disables the Autobaud Mode, clearing the ABM field in the
CAN_MR register.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
495