SAM7X256_14 Datasheet, PDF (224/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle
the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be
visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed
1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising
edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in
Figure 27-5.
The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter
Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and
clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value
read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is
enabled.
Figure 27-5. Input Glitch Filter Timing
MCK
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle 1 cycle
up to 1.5 cycles
1 cycle
2 cycles
up to 2.5 cycles
1 cycle
1 cycle
up to 2 cycles
27.4.10 Input Change Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input
Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register),
which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in
PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings
of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless
of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a
peripheral function.
When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If
the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two
channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller.
When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that
are pending when PIO_ISR is read must be handled.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
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