SAM7X256_14 Datasheet, PDF (644/662 Pages) ATMEL Corporation – ARM-based Flash MCU

41.7.7 Serial Peripheral Interface (SPI)
41.7.7.1 SPI: Bad Serial Clock Generation on 2nd Chip Select
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
 Master Mode
 CPOL = 1 and NCPHA = 0
 Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock frequency
equals the system clock frequency) and the other transfers set with SCBR are not equal to 1
 Transmitting with the slowest chip select and then with the fastest one, then an additional pulse is generated on
output SPCK during the second transfer.
Problem Fix/Workaround
Do not use a multiple Chip Select configuration where at least one SCRx register is configured with SCBR = 1 and the
others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
41.7.8 Universal Synchronous Asynchronous Receiver Transmitter (USART)
41.7.8.1 USART: DCD is Active High instead of Low
The DCD signal is active at High level in the USART Modem Mode.
DCD should be active at Low level.
Problem Fix/Workaround
Add an inverter.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
644