SAM7X256_14 Datasheet, PDF (172/662 Pages) ATMEL Corporation – ARM-based Flash MCU

25. Power Management Controller (PMC)
25.1
Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral
clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor.
The Power Management Controller provides the following clocks:
 MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device.
It is available to the modules running permanently, such as the AIC and the Memory Controller.
 Processor Clock (PCK), switched off when entering processor in idle mode.
 Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, MCI, etc.)
and independently controllable. In order to reduce the number of clock names in a product, the Peripheral Clocks
are named MCK in the product datasheet.
 UDP Clock (UDPCK), required by USB Device Port operations.
 Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the
PCKx pins.
25.2
Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all
the peripherals and the memory controller.
The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides
a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLL.
The Master Clock Controller is made up of a clock selector and a prescaler.
The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock
Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The PRES field in
PMC_MCKR programs the prescaler.
Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until
the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature
is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done.
Figure 25-1.
Master Clock Controller
PMC_MCKR
CSS
SLCK
MAINCK
PLLCK
PMC_MCKR
PRES
Master Clock
Prescaler
MCK
To the Processor
Clock Controller (PCK)
25.3
Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock
can be disabled by writing the System Clock Disable Register (PMC_SCDR). The status of this clock (at least for debug
purpose) can be read in the System Clock Status Register (PMC_SCSR).
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
172