SAM7X256_14 Datasheet, PDF (42/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Table 11-2.
Mnemonic
LDR
LDRSH
LDRSB
LDRH
LDRB
LDRBT
LDRT
LDM
SWP
MCR
LDC
ARM Instruction Mnemonic List
Operation
Load Word
Load Signed Halfword
Load Signed Byte
Load Half Word
Load Byte
Load Register Byte with Translation
Load Register with Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Mnemonic
SWI
STR
STRH
STRB
STRBT
STRT
STM
SWPB
MRC
STC
Operation
Software Interrupt
Store Word
Store Half Word
Store Byte
Store Register Byte with Translation
Store Register with Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
11.2.6 Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
 Branch instructions
 Data processing instructions
 Load and Store instructions
 Load and Store Multiple instructions
 Exception-generating instruction
In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as R0 to
R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15),
the Link Register (ARM Register 14) and the Stack Pointer (ARM Register 13). Further instructions allow limited access
to the ARM registers 8 to 15.
Table 11-3 gives the Thumb instruction mnemonic list.
Table 11-3.
Mnemonic
MOV
ADD
SUB
CMP
TST
AND
EOR
LSL
ASR
MUL
B
BX
Thumb Instruction Mnemonic List
Operation
Move
Add
Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Logical Shift Left
Arithmetic Shift Right
Multiply
Branch
Branch and Exchange
Mnemonic
MVN
ADC
SBC
CMN
NEG
BIC
ORR
LSR
ROR
BL
SWI
Operation
Move Not
Add with Carry
Subtract with Carry
Compare Negated
Negate
Bit Clear
Logical (inclusive) OR
Logical Shift Right
Rotate Right
Branch and Link
Software Interrupt
SAM7X Series [DATASHEET] 42
6120K–ATARM–11-Feb-14