SAM7X256_14 Datasheet, PDF (298/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 30-4. Fractional Baud Rate Generator
FP
USCLKS
MCK
0
MCK/DIV
1
Reserved
SCK
2
3
Modulus
CD
Control
16-bit Counter
FP
CD
glitch-free
logic
>1
1
0
0
0
1
SYNC
USCLKS = 3
FIDI
OVER
Sampling
Divider
SCK
SYNC
0
Baud Rate
Clock
1
Sampling
Clock
30.6.1.4 Baud Rate in Synchronous Mode
If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in
US_BRGR.
BaudRate = ^S----^e---^l--^e---^c---^t--^e---^d---^C-----^l--^o---^c---^k-
CD
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the
USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must
be at least 4.5 times lower than the system clock.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD
must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the
Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.
30.6.1.5 Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
B = ^D-----ⁱ × f
Fi
where:
 B is the bit rate
 Di is the bit-rate adjustment factor
 Fi is the clock frequency division factor
 f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 30-3.
Table 30-3. Binary and Decimal Values for Di
DI field
0001
0010
0011
Di (decimal)
1
2
4
0100
8
0101
16
0110
32
1000
12
1001
20
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
298