SAM7X256_14 Datasheet, PDF (640/662 Pages) ATMEL Corporation – ARM-based Flash MCU

41.6.9.3 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as an input and TF is programmed as an output and requested to be set to low/high during data
emission, the Frame Synchro signal is generated one bit clock period after the data start and one data bit is lost. This
problem does not exist when generating a periodic synchro.
Problem Fix/Workaround
The data need to be delayed for one bit clock period with an external assembly. In the following schematic, TD, TK and
NRST are AT91SAM7X signals, TXD is the delayed data to connect to the device.
41.6.10 Two-wire Interface (TWI)
41.6.10.1 TWI: Clock Divider
The value of CLDIV x 2^CKDIV must be less than or equal to 8191, the value of CHDIV x 2^CKDIV must be less than or equal
to 8191⋅
Problem Fix/Workaround
None.
41.6.10.2 TWI: Disabling Does not Operate Correctly
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1.
Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled before
disabling the TWI.
41.6.10.3 TWI: NACK Status Bit Lost
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit rising
in the TWI_SR, the NACK bit is not set.
Problem Fix/Workaround
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission is not
completed.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
640