SAM7X256_14 Datasheet, PDF (492/662 Pages) ATMEL Corporation – ARM-based Flash MCU

36.6.4.5 Fault Confinement
To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive
Error Counter) and TEC (Transmit Error Counter). The two counters are incremented upon detected errors and are
decremented upon correct transmissions or receptions, respectively. Depending on the counter values, the state of the
node changes: the initial state of the CAN controller is Error Active, meaning that the controller can send Error Active
flags. The controller changes to the Error Passive state if there is an accumulation of errors. If the CAN controller fails or
if there is an extreme accumulation of errors, there is a state transition to Bus Off.
Figure 36-7. Line Error Mode
Init
TEC < 127
and
REC < 127
ERROR
PASSIVE
ERROR
ACTIVE
128 occurences of 11 consecutive recessive bits
or
CAN controller reset
TEC >127
or
REC > 127
BUS OFF
TEC > 255
An error active unit takes part in bus communication and sends an active error frame when the CAN controller detects an
error.
An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is
detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating further
transmission.
A bus off unit is not allowed to have any influence on the bus.
For fault confinement, two errors counters (TEC and REC) are implemented. These counters are accessible via the
CAN_ECR register. The state of the CAN controller is automatically updated according to these counter values. If the
CAN controller is in Error Active state, then the ERRA bit is set in the CAN_SR register. The corresponding interrupt is
pending while the interrupt is not masked in the CAN_IMR register. If the CAN controller is in Error Passive Mode, then
the ERRP bit is set in the CAN_SR register and an interrupt remains pending while the ERRP bit is set in the CAN_IMR
register. If the CAN is in Bus Off Mode, then the BOFF bit is set in the CAN_SR register. As for ERRP and ERRA, an
interrupt is pending while the BOFF bit is set in the CAN_IMR register.
When one of the error counters values exceeds 96, an increased error rate is indicated to the controller through the
WARN bit in CAN_SR register, but the node remains error active. The corresponding interrupt is pending while the
interrupt is set in the CAN_IMR register.
Refer to the Bosch CAN specification v2.0 for details on fault confinement.
36.6.4.6 Error Interrupt Handler
WARN, BOFF, ERRA and ERRP (CAN_SR) represent the current status of the CAN bus and are not latched. They
reflect the current TEC and REC (CAN_ECR) values as described in Section 36.6.4.5 “Fault Confinement” on page 492.
Based on that, if these bits are used as an interrupt, the user can enter into an interrupt and not see the corresponding
status register if the TEC and REC counter have changed their state. When entering Bus Off Mode, the only way to exit
from this state is 128 occurrences of 11 consecutive recessive bits or a CAN controller reset.
In Error Active Mode, the user reads:
 ERRA =1
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
492