SAM7X256_14 Datasheet, PDF (435/662 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 34-5. Setup Transaction Followed by a Data OUT Transaction
Setup Received
Setup Handled by Firmware
Data Out Received
USB
Bus Packets
Setup
PID
Data Setup
ACK
PID
Data OUT
PID
Data OUT
NAK
PID
Data OUT
PID
Data OUT
ACK
PID
RXSETUP Flag
RX_Data_BKO
(UDP_CSRx)
Interrupt Pending
Set by USB Device
Cleared by Firmware
Set by USB
Device Peripheral
FIFO (DPR)
XX
Content
Data Setup
XX
Data OUT
34.5.2.2 Data IN Transaction
Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from
the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong
attributes.
Using Endpoints Without Ping-pong Attributes
To perform a Data IN transaction using a non ping-pong endpoint:
1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_ CSRx
register (TXPKTRDY must be cleared).
2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in
the endpoint’s UDP_ FDRx register,
3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_ CSRx
register.
4. The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the
endpoint’s UDP_ CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while
TXCOMP is set.
5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more byte
values in the endpoint’s UDP_ FDRx register,
6. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_
CSRx register.
7. The application clears the TXCOMP in the endpoint’s UDP_ CSRx.
After the last packet has been sent, the application must clear TXCOMP once this has been set.
TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is
pending while TXCOMP is set.
Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN proto-
col layer.
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
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