SAM7X256_14 Datasheet, PDF (632/662 Pages) ATMEL Corporation – ARM-based Flash MCU

The data need to be delayed for one bit clock period with an external assembly. In the following schematic, TD, TK and
NRST are AT91SAM7X signals, TXD is the delayed data to connect to the device.
41.5.9 Two-wire Interface (TWI)
41.5.9.1 TWI: Clock Divider
The value of CLDIV x 2^CKDIV must be less than or equal to 8191, the value of CHDIV x 2^CKDIV must be less than or equal
to 8191⋅
Problem Fix/Workaround
None.
41.5.9.2 TWI: Disabling Does not Operate Correctly
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1.
Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled before
disabling the TWI.
41.5.9.3 TWI: NACK Status Bit Lost
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit rising
in the TWI_SR, the NACK bit is not set.
Problem Fix/Workaround
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission is not
completed.
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR.
41.5.9.4 TWI: Possible Receive Holding Register Corruption
When loading the TWI_RHR, the transfer direction is ignored. The last data byte received in the TWI_RHR is corrupted
at the end of the first subsequent transmit data byte. Neither RXRDY nor OVERRUN status bits are set if this occurs.
Problem Fix/Workaround
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
632