|
SAM7X256_14 Datasheet, PDF (650/662 Pages) ATMEL Corporation – ARM-based Flash MCU | |||
|
◁ |
Version
6120G
(Continued) Comments
Change
Request
Ref.
SPI,
Section 28.6.4 âSPI Slave Modeâ on page 254, corrected information on OVRES (SPI_SR) and data read in
SPI_RDR.
3943
SSC,
Section 31.6.5.1 âFrame Sync Dataâ, defined max Frame Sync Data length.
Section 31.6.6.1 âCompare Functionsâ, updated with max FSLEN length.
2293
TC,
Figure 32-2,âClock Chaining Selectionâ, added to Section 32.5 âFunctional Descriptionâ.
Section 32.6 âTimer Counter (TC) User Interfaceâ Register mapping tables consolidated in Table 32-4 on page
389 and register offsets indexed.
3342
4583
Section 32.6.3 on page 392 to Section 32.6.13 on page 406, register names updated with indexed offset.
Section 32.6.4 âTC Channel Mode Register: Capture Modeâ bit field 15 and WAVE bit field description updated.
TWI,
âTwo-wire Interface (TWI)â , section has been updated.
Important changes to this datasheet include a clarification of Atmel TWI compatibility with I2C Standard.
4247
UDP,
Table 34-2, âUSB Communication Flowâ, Supported Endpoint column updated.
In the USB_CSR register, the control endpoints are not effected by the bit field, âEPEDS: Endpoint Enable
Disableâ on page 475
Updated: write 1 =.... in âRX_DATA_BK0: Receive Data Bank 0â bit field of USB_CSR register.
Updated: write 0 = ....in âTXPKTRDY: Transmit Packet Readyâ bit field of USB_CSR register.
3476
4063
4099
Section 34.6.10 âUDP Endpoint Control and Status Registerâ on page 457, update to code and added
4462
instructions regarding USB clock and system clock cycle, and updated ânoteâ appearing under the code.
4487
âwait 3 USB clock cycles and 3 system clock cycles before accessing DPR from RX_DATAx and TXPKTRDY bit
fields, ditto for RX_DATAx and TXPKTRDY bit field descriptions.â
4508
Section 34.2 âBlock Diagramâ, in the text below the block diagram, MCK specified as clock used by Master Clock
domain, UDPCK specified as 48 MHz clock used by 12 MHz domain, in peripheral clock requirements.
Section 34.6 âUSB Device Port (UDP) User Interfaceâ, The register mapping table has been updated
Section 34.6.6 âUDP Interrupt Mask Registerâ Bit 12 of has been defined as BIT12 and cannot be masked.
4802
USART,
âCLKO: Clock Output Selectâ on page 323, bit field in US_MR register, typo fixed in bit field description.
3306
âUSCLKS: Clock Selectionâ on page 321, bit field in US_MR register, DIV= 8 in Selected Clock column.
3763
Section 30.5.1 âI/O Linesâ, 2nd and 3rd paragraphsupdated.
3851/4285
âTXEMPTY: Transmitter Emptyâ on page 328, no characters when at 1 updated.
3895
Section 30.6.2 âReceiver and Transmitter Controlâ, In the fourth paragraph, Software reset effects (RSTRX and 4367
RSTTX in US_CR register) updated by replacing 2nd sentence.
Section 30.6.5 âIrDA Modeâ, updated with instruction to receive IrDA signals.
Section 30.2 âBlock Diagramâ, signal directions from pads to PIO updated in the block diagram.
4912
4905
SAM7X Series [DATASHEET]
6120KâATARMâ11-Feb-14
650
|
▷ |