SAM7X256_14 Datasheet, PDF (273/662 Pages) ATMEL Corporation – ARM-based Flash MCU

29.5.4 Master Receiver Mode
The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit
slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case
(MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH),
enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the
master sends an acknowledge condition to notify the slave that the data has been received except for the last data, after
the stop condition. See Figure 29-9. When the RXRDY bit is set in the status register, a character has been received in
the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be
set at the same time. See Figure 29-8. When a multiple data byte read is performed, with or without internal address
(IADR), the STOP bit must be set after the next-to-last data received. See Figure 29-9. For Internal Address usage see
Section 29.5.5.
Figure 29-8. Master Read with One Data Byte
TWD
S
DADR
RA
DATA
NP
TXCOMP
RXRDY
Write START &
STOP Bit
Read RHR
Figure 29-9. Master Read with Multiple Data Bytes
TWD S
DADR
RA
DATA n
A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P
TXCOMP
RXRDY
Write START Bit
Read RHR
DATA n
Read RHR
DATA (n+1)
Read RHR
DATA (n+m)-1
Read RHR
DATA (n+m)
Write STOP Bit
after next-to-last data read
SAM7X Series [DATASHEET]
6120K–ATARM–11-Feb-14
273