SAM7X256_14 Datasheet, PDF (59/662 Pages) ATMEL Corporation – ARM-based Flash MCU

13.2.4.2 User Reset
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The
NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset
are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three-cycle processor startup.
The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the
value 0x4, indicating a User Reset.
The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as
programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is
driven low externally, the internal reset lines remain asserted until NRST actually rises.
Figure 13-5. User Reset State
SLCK
MCK
NRST
proc_nreset
RSTTYP
periph_nreset
Any
Freq.
Resynch.
2 cycles
Any
Resynch.
2 cycles
Processor Startup
= 3 cycles
XXX
0x4 = User Reset
NRST
(nrst_out)
>= EXTERNAL RESET LENGTH
SAM7X Series [DATASHEET] 59
6120K–ATARM–11-Feb-14