SAM7X256_14 Datasheet, PDF (253/662 Pages) ATMEL Corporation – ARM-based Flash MCU

The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode
Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is
destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and
LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO
and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the
buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the
processor.
28.6.3.6 Peripheral Chip Select Decoding
The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to
NPCS3 with an external logic. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR).
When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven
low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or
the Transmit Data Register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any
transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the
characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded
peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible
peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
28.6.3.7 Peripheral Deselection
When operating normally, as soon as the transfer of the last data written in SPI_TDR is completed, the NPCS lines all
rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to
difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of
transfers.
To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSAAT bit (Chip Select
Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to
another peripheral is required.
Figure 28-8 shows different peripheral deselection cases and the effect of the CSAAT bit.
SAM7X Series [DATASHEET]
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