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SAM7X256_14 Datasheet, PDF (426/662 Pages) ATMEL Corporation – ARM-based Flash MCU | |||
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33.6.11 PWM Channel Period Register
Register Name:
PWM_CPRD[0. X-1]
Access Type:
Read-write
31
30
29
28
27
26
25
24
CPRD
23
22
21
20
19
18
17
16
CPRD
15
14
13
12
11
10
9
8
CPRD
7
6
5
4
3
2
1
0
CPRD
Only the first 16 bits (internal channel counter size) are significant.
⢠CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated:
â By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
(---X-----Ã-----C----P----R----D-----)
MCK
â By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(---C----R----P----D------Ã-----D-----I--V----A----)-
MCK
or
(---C----R----P----D------Ã-----D-----I--V----A----B----)-
MCK
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated:
â By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
256, 512, or 1024). The resulting period formula will be:
(---2----Ã-----X-----Ã-----C-----P----R----D----)-
MCK
â By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
(---2----Ã-----C-----P----R----D------Ã----D-----I--V----A----)- or (---2----Ã-----C-----P----R----D-----Ã-----D-----I--V----B----)-
MCK
MCK
SAM7X Series [DATASHEET]
6120KâATARMâ11-Feb-14
426
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