AK8186B Datasheet, PDF (9/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

Parameter
Conditions
Min
Prescaler (Part of N divider)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
1E1[1]=0
1E1[1]=0
1E1[1]=0
1E1[1]=0
1E1[1]=0
1E1[1]=0 or 1
1E1[1]=0 or 1
1E1[1]=0 or 1
A,B counter input.
Noise Characteristics
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detecter
@500 kHz PFD Frequency
@1MHz PFD Frequency
@10MHz PFD Frequency
@50MHz PFD Frequency
PLL Figure of Merit (FOM)
FOM
= Phase Noise - 10log(fPFD)
- 20log(Ndiv) + 20log(Odiv);
where Ndiv = N divider ratio, Odiv =
VCO divider ratio * Channel divider
ratio.
PLL Digital Lock Detect Window
Required to Lock
To Unlock After Lock (Hysteresis)
0x18[4] = 1
0x18[4] = 0
0x18[4] = 1
0x18[4] = 0
*1) [(|Isink|-|Isource|)/{(|Isink|+|Isource|)/2}] * 100 [%]
*2) (|I1-I2|)/(|I1+I2|/2)*100 [%]
Clock Input Characteristics
Table 5.
Parameter
CLOCK INPUTS (CLK, )
Input Frequency
Input Sensitivity, Differential
Input Level, Differential
Input Common-Mode Voltage, Vcm
Input Common-Mode Range, Vcm
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Conditions
Min
Below 1MHz should be dc-coupled.
0
1.3
With 200mVpp signal applied.
1.3
dc-coupled
CLK ac-coupled,
CLK ac-bypassed to RF ground.
Self-biased
3.2
AK8186B
Typ
Max
Unit
300
500
500
500
500
2250
2250
2250
300
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
-169
dBc/Hz
-166
dBc/Hz
-155
dBc/Hz
-147
dBc/Hz
-226
dBc/Hz
3.5
ns
7.5
ns
7
ns
15
ns
Typ
Max
Unit
500
MHz
150
mVpp
2
Vpp
1.57
1.8
V
1.8
V
150
mVpp
4.7
6.1
kΩ
2
pF
draft-E-02
Sep-2012
-9-