AK8186B Datasheet, PDF (60/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Register
Address Bit(s)
(Hex)
Name
0x143
OUT9 LVDS
2:1 Output
Current
OUT9
0 _Power-Down
Description
Sets output current level in LVDS mode. This has no effect CMOS mode,
[2:1] Current (mA) Recommend Termination (Ω)
0 0 1.75
100
0 1 3.5
100 (default)
1 0 5.25
50
1 1 7.0
50
Power-down output(LVDS/CMOS).
0: Power on.
1: Power off. (default) LVDS: Outputs Hi-Z CMOS: Outputs Low
LVPECL Channel Dividers
Register
Address
(Hex)
0x190
Bit(s)
Name
Divider 0
7:4 _{Low Cycles M}
Divider 0
3:0 _{High Cycles N}
Divider 0
7 _Bypass
Divider 0
6 Nosync
0x191
Divider 0
5 _{Force High}
Divider 0
4 _{Start High}
0x193
Divider 0
3:0 _{Phase Offset}
Divider 1
7:4 _{Low Cycles M}
Divider 1
3:0 _{High Cycles N}
Divider 1
7 _Bypass
0x194
Divider 1
6 Nosync
Divider 1
5 _{Force High}
Description
Number of Low clock cycles (M) and High clock cycles (N) of the divider input
define a frequency division, Dx, of the Divider 0. Dx = M+N+2.
Note) The M and N does not affect the duty of LVPECL output. The DCC(Duty Cycle
Correction) always works.
Bypasses and power-down the divider; route input to divider output.
0: use divider.
1: bypass divider. (default)
Nosync.
0: obey chip-level SYNC signal. (default)
1: ignore chip-level SYNC signal.
Forces divider output to high. This requires that nosync also be set.
0: divider output force to low. (default)
1: divider output force to high.
Selects clock output to start high or start low.
0: start low. (default)
1: start high.
Phase offset. (default=0x0)
Number of Low clock cycles (M) and High clock cycles (N) of the divider input
define a frequency division, Dx, of the Divider 1. Dx = M+N+2.
Note) The M and N does not affect the duty of LVPECL output. The DCC(Duty Cycle
Correction) always works.
Bypasses and power-down the divider; route input to divider output.
0: use divider. (default)
1: bypass divider.
Nosync.
0: obey chip-level SYNC signal. (default)
1: ignore chip-level SYNC signal.
Forces divider output to high. This requires that nosync also be set.
0: divider output force to low. (default)
1: divider output force to high.
Sep-2012
- 60 -
draft-E-02