AK8186B Datasheet, PDF(2/69 Page) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

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AK8186B Datasheet, PDF (2/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

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AK8186B

BLOCK DIAGRAM

REF_SEL

RSET

REFMON

REFIN/REF1

REFIN/REF2

REF1

REF2

REFERENCE

SWITCHOVER

STATUS

BYPASS

LDO

DISTRIBUTION

REFERENCE

DIVIDER

P,P+1

PRESCALER

N DIVIDER

A/B

COUNTER

VCO STATUS

VCO

CLK

VCO Divider

DIVIDE by

2 to 6

Divider 0

DIVIDE by

1 to 32

Divider 1

DIVIDE by

1 to 32

CPRSET

PLL

REFERENCE

LOCK

DETECT

PHASE

FREQUENCY

DETECTOR

HOLD

CHARGE

PUMP

LVPECL

SYNC

RESET

SCLK

SDIO

SDO

DIGITAL

LOGIC

SERIAL

CONTROL

PORT

Divider 2

DIVIDE by

1 to 32

Divider 3.1

DIVIDE by

1 to 32

Divider 4.1

DIVIDE by

1 to 32

Divider 3.2

DIVIDE by

1 to 32

Divider 4.2

DIVIDE by

1 to 32

LVDS/ï¼CMOSï¼

STATUS

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

Figure 1. AK8186B Block Diagram

Sep-2012

draft-E-02

-2-

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