AK8186B Datasheet, PDF (25/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Since the maximum output frequency of the prescaler is 300MHz, the prescaler input frequency is limited by
the modes as shown in Table 4. The prescaler must divide its input frequency by appropriate divide ratio
defined by Register 0x016[2:0]. In case of using the internal VCO, its output (1.75GHz min) must be
divided by P = 8, 16 and 32. (See the “PLL Configuration in Register Map Function Descriptions”)
FD mode (A=0)
The Prescaler divider value is P. It is divided by B counter.
N=PxB
Where P = 1, 2, 4, 8, 16 or 32 for an external VCO/VCXO.
P = 8, 16 or 32 for an internal VCO.
B : 3 to 8191 when B = 1, B counter is bypassed. Not allowed for B = 0 and 2.
DM mode (A0)
The prescaler divider value is P for (B-A) times and P+1 for A times.
N=PxB+A
Where P = 1, 2/3, 4/5, 8/9, 16/17 or 32/33 for an external VCO/VCXO.
P = 8/9, 16/17 or 32/33 for an internal VCO.
B : 3 to 8191 when B = 1, B counter is bypassed. Not allowed for B = 0 and 2.
The output frequency of the N divider f_VCO/N is equated to the output of the R divider f_REF/R at the PFD.
Then the VCO frequency is
1) When A = 0: f_VCO = f_REF x N/R where N = P x B
2) When A  0: f_VCO = f_REF x N/R where N = P x B + A
A and B COUNTERS
The division value of the A and B counters is defined by the registers below.
A counter : 0x13[5:0]
B counter : 0x14[7:0] and 0x15[4:0]
Note;
- Both division values should be set A ≤ B.
- P = 1, 2, 4, 8, 16 or 32 when A=0.
- B = 0 and B = 2 are not allowed.
- Maximum input frequency of A/B counters is 300MHz.
Reset Counters
SYNC pin resets all of P, A and B counters simultaneously. This is allowed by the register 0x19[7:6].
A/B counters can be reset by the register 0x16[5][4].
draft-E-02
- 25 -
Sep-2012