AK8186B Datasheet, PDF (11/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Timing Characteristics
Table 7. All specifications at VDD=3.3V5%, VDD_LVPECL= 2.375V to VDD, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN
TYP
MAX
LVPECL Output
Rise/Fall time
Propagation Delay,
CLK-to-LVPECL Ouput
Variation with Temperature
Output Skew ^*1
Output Duty
LVDS Output
Rise/Fall time
Propagation Delay,
CLK-to-LVPECL Ouput
Variation with Temperature
Output Skew ^*1
Output Duty
Termination =
50Ω to VDD-LVPECL-2V
0xFn[3:2] = 10 (n=0 to 5)
20% to 80% / 80% to 20%
Same Divider
Different Dividers
750MHz ≤ Fout
30
500M ≤ Fout < 750MHz
35
250M ≤ Fout < 500MHz ^*2
40
Fout < 250MHz ^{*2 *3}
45
Fout<1000MHz, VDD_LVPECL=3.3V5%
45
Termination = 100Ω @3.5mA
0x14n[2:1] = 01 (n=0 to 3)
20% to 80% / 80% to 20%
For All Device Values
Same Divider
Different Dividers
*2 *3
45
175
225
TBD
TBD
5
40
13
40
50
70
50
65
50
60
50
55
50
55
190
350
TBD
TBD
6
62
25
150
50
55
CMOS Output
20% to 80% / 80% to 20%
Rise/Fall time
Cload = 10pF
400
1000
Propagation Delay,
CLK-to-LVPECL Ouput
Variation with Temperature
Output Skew ^*1
For All Device Values
Same Divider
Different Dividers
TBD
TBD
4
66
28
180
Output Duty
*2 *3
45
50
55
*1) Skew: The Difference between any two similar delay paths while operating at the same voltage and temperature.
_______
*2) Differential input through CLK/CLK pins: Clock input is assumed to be 50% duty.
*3) Single-end input through CLK pin: Clock input is assumed to be 50% duty and Fout < 150 MHz.
Unit
ps
ns
ps/C
ps
ps
%
%
%
%
%
ps
ns
ps/C
ps
ps
%
ps
ns
ps/C
ps
ps
%
draft-E-02
- 11 -
Sep-2012