AK8186B Datasheet, PDF (12/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used)
Table 8. All specifications at VDD=3.3V5%, VDD_LVPECL= 2.375V to VDD, Ta: -40 to +85℃, unless otherwise noted
Parameter
Min
CLK-TO-LVPECL Additive Phase Noise
CLK=500MHz, Output=500MHz,
Divider=1
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
CLK=500MHz, Output=250MHz,
Divider=2
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
CLK-TO-LVDS Additive Phase Noise
CLK=500MHz, Output=500MHz,
Divider=1
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
CLK=500MHz, Output=250MHz,
Divider=2
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
Typ
-108
-130
-142
-149
-150
-114
-133
-143
-151
-152
-106
-126
-141
-145
-147
-114
-133
-143
-150
-152
Max
Unit
Test Conditions/Comments
Does not include PLL and VCO
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Does not include PLL and VCO
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Sep-2012
- 12 -
draft-E-02