AK8186B Datasheet, PDF (58/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
LVDS/CMOS Outputs
Register
Address Bit(s)
(Hex)
Name
OUT6 Output
7:5 _Polarity
0x140
4 OUT6 CMOS B
OUT6 Select
3 LVDS/CMOS
OUT6 LVDS
2:1 Output
Current
OUT6
0 _Power-Down
OUT7 Output
7:5 _Polarity
0x141
4 OUT7 CMOS B
OUT7 Select
3 LVDS/CMOS
OUT7 LVDS
2:1 Output
Current
Description
In CMOS mode,[7:5] select the output polarity of each CMOS output.
In LVDS mode, only [5] determines LDVS polarity.
[7:6:5] OUT6(CMOS) OUT6n(CMOS) OUT6(LVDS)
0 0 0 Non-inverting. Inverting.
Non-inverting.
0 1 0 Non-inverting. Non-inverting.
Non-inverting (default)
1 0 0 Inverting.
Inverting.
Non-inverting
1 1 0 Inverting.
Non-inverting.
Non-inverting
0 0 1 Inverting.
Non-inverting.
Inverting
0 1 1 Inverting.
Inverting.
Inverting
1 0 1 Non-inverting. Non-inverting.
Inverting
1 1 1 Non-inverting. Inverting.
Inverting
In CMOS mode, turn on/off the OUT6n output. There is no effect in LDVS
mode.
0: turn off the OUT6n output. (default)
1: turn on the OUT6n output..
Selects LVDS or CMOS logic levels.
0: LVDS. (default)
1: CMOS.
Sets output current level in LVDS mode. This has no effect CMOS mode,
[2:1] Current (mA) Recommend Termination (Ω)
0 0 1.75
100
0 1 3.5
100 (default)
1 0 5.25
50
1 1 7.0
50
Power-down output(LVDS/CMOS).
0: Power on.
1: Power off. (default) LVDS: Outputs Hi-Z CMOS: Outputs Low
In CMOS mode,[7:5] select the output polarity of each CMOS output.
In LVDS mode, only [5] determines LDVS polarity.
[7:6:5] OUT7(CMOS) OUT7n(CMOS) OUT7(LVDS)
0 0 0 Non-inverting. Inverting.
Non-inverting.
0 1 0 Non-inverting. Non-inverting.
Non-inverting (default)
1 0 0 Inverting.
Inverting.
Non-inverting
1 1 0 Inverting.
Non-inverting.
Non-inverting
0 0 1 Inverting.
Non-inverting.
Inverting
0 1 1 Inverting.
Inverting.
Inverting
1 0 1 Non-inverting. Non-inverting.
Inverting
1 1 1 Non-inverting. Inverting.
Inverting
In CMOS mode, turn on/off the OUT7n output. There is no effect in LDVS
mode.
0: turn off the OUT7n output. (default)
1: turn on the OUT7n output..
Selects LVDS or CMOS logic levels.
0: LVDS. (default)
1: CMOS.
Sets output current level in LVDS mode. This has no effect CMOS mode,
[2:1] Current (mA) Recommend Termination (Ω)
0 0 1.75
100
0 1 3.5
100 (default)
1 0 5.25
50
1 1 7.0
50
Sep-2012
- 58 -
draft-E-02