AK8186B Datasheet, PDF (15/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

Clock Output Additive Time Jitter (VCO Divider Not Used)
AK8186B
Table 12
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL Output Additive Time Jitter
CLK=500MHz,Output=500MHz,Divider=1
CLK=500MHz,Output=250MHz,Divider=2
CLK=500MHz,Output=100MHz,Divider=5
LVDS Output Additive Time Jitter
CLK=500MHz,Output=500MHz,Divider=1
CLK=500MHz,Output=250MHz,Divider=2
CLK=500MHz,Output=100MHz,Divider=5
CMOS Output Additive Time Jitter
CLK=500MHz,Output=100MHz,Divider=5
Distribution Section Only
39
fs rms 12kHz to 20MHz
92
fs rms 12kHz to 20MHz
137
fs rms 12kHz to 20MHz
Distribution Section Only
76
fs rms 12kHz to 20MHz
92
fs rms 12kHz to 20MHz
237
fs rms 12kHz to 20MHz
Distribution Section Only
131
fs rms 12kHz to 20MHz
Clock Output Additive Time Jitter (VCO Divider Used)
Table 13
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL Output Additive Time Jitter
CLK=500MHz,Output=100MHz,Divider=5
Distribution Section Only
129
fs rms 12kHz to 20MHz
LVDS Output Additive Time Jitter
CLK=500MHz,Output=100MHz,Divider=5
Distribution Section Only
219
fs rms 12kHz to 20MHz
CMOS Output Additive Time Jitter
CLK=500MHz,Output=100MHz,Divider=5
Distribution Section Only
120
fs rms 12kHz to 20MHz
draft-E-02
- 15 -
Sep-2012