AK8186B Datasheet, PDF (47/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

PLL Configuration
AK8186B
Register
Address Bit(s)
(Hex)
Name
Description
7 PFD Polarity
Sets the PFD Polarity. The on-chip VCO requires positive polarity.
0 : Positive ; higher control voltage produces higher frequency (default)
1 : Negative; higher control voltage produces lower frequency
6:4 CP Current
0x010
3:2 CP Mode
Charge Pump current (with CPRSET=5.1kΩ).
[6:5:4] Icp(mA)
0 0 0 0.6
0 0 1 1.2
0 1 0 1.8
0 1 1 2.4
1 0 0 3.0
1 0 1 3.6
1 1 0 4.2
1 1 1 4.8 (default)
Charge pump operating mode.
[3:2] Charge pump mode
0 0 High impedance state
0 1 Force source current (pump up)
1 0 Force sink current(pump down)
1 1 Normal operation. (default)
PLL
1:0 _{Power Down}
PLL operating mode.
[1:0] PLL Mode
0 0 Normal operation.
0 1 Asynchronous power-down. (default)
1 0 Normal operation.
1 1 Synchronous power-down.
14-Bit R Divider
0x011 7:0 _{Bits[7:0] (LSB)} R divider LSBs, lower eight bits (default=0x01).
14-Bit R Divider
0x012 5:0 _{Bits[13:8] (MSB)} R divider MSBs, upper six bits (default=0x00).
0x013
0x014
0x015
5:0 6-Bit A Counter A counter (part of N divider) (default=0x00).
13-Bit B Counter
7:0 _Bits[7:0]
B counter (part of N divider). Lower eight bits (default=0x03).
13-Bit B Counter
4:0 _Bits[12:8]
B counter (part of N divider). Upper eight bits (default=0x00).
0x016
Set CP pin
7 _{To VDD/2}
Rest R
6 _Counters
Sets the CP pin to one-half of the VDD supply voltage.
0: CP normal operation (default).
1: CP pin set to VDD/2.
Resets R counter (R divider)
0: normal (default)
1: reset R counter.
draft-E-02
- 47 -
Sep-2012