AK8186B Datasheet, PDF (49/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Register
Address Bit(s)
(Hex)
Name
STATUS
0x017 7:2 _{Pin Control}
Lock Detect
6:5 _Counter
0x018
Digital Lock
4 _{Detect Window}
Description
[7:6:5:4:3:2]
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Level or
Dynamic
Signals
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Signal at STATUS Pin
Status REF2 frequency. (active high)
(Status REF1 Freq.) AND (Status REF2 Freq.)
(DLD) AND (Status of selected reference)
AND (status of VCO)
Status of VCO Frequency (active high)
Selected reference (Low=REF1,High=REF2)
Digital Lock Detect(DLD); active High
Holdover active(active high)
LD pin comparator output (active high).
VDD (PLL supply)
(REF1 Clock)n
(REF2 Clock)n
(Selected reference to PLL)n
(Unselected reference to PLL)n
Status of selected reference: active low
Status of unselected reference: active low
Status of REF1 frequency(active low)
Status of REF2 frequency(active low)
((Status REF1 Freq.) AND (Status REF2 Freq.))n
((DLD) AND (Status of selected reference)
AND (status of VCO))n
Status of VCO Frequency (Active low)
Selected reference (Low=REF2,High=REF1).
Digital Lock Detect(DLD): Active Low
Holdover active(active low)
LD Pin comparator output(Active low)
[6:5]
00
01
10
11
PFD Cycles Determine Lock
5 (default)
16
64
255
Digital Lock Detect Window Size
Lock Unlock
0 : High Range 7.5ns 15ns (default)
1 : Low Range 3.5ns 7ns
draft-E-02
- 49 -
Sep-2012