AK8186B Datasheet, PDF (62/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
LVDS/CMOS Channel Dividers
Register
Address
(Hex)
0x199
Bit(s)
Name
Divider 3.1
7:4 _{Low Cycles M}
Divider 3.1
3:0 _{High Cycles N}
0x19A
Divider 3.2
7:4 _{Phase Offset}
Divider 3.1
3:0 _{Phase Offset}
0x19B
Divider 3.2
7:4 _{Low Cycles}
Divider 3.2
3:0 _{High Cycles}
Divider 3.2
5 _Bypass
Divider 3.1
4 _Bypass
0x19C
Divider 3
3 _Nosync
Divider 3
2 _{Force High}
Divider 3.2
1 _{Start High}
Divider 3.1
0 _{Start High}
Description
Number of Low clock cycles (M) and High clock cycles (N) of the divider input
define a frequency division, Dx, of the Divider 3.1. Dx = M+N+2.
Note) The M and N does not affect the duty of LVDS/CMOS output. The DCC(Duty Cycle
Correction) always works.
Refer to LVDS/CMOS channel divider function description.
Refer to LVDS/CMOS channel divider function description.
Number of Low clock cycles (M) and High clock cycles (N) of the divider input
define a frequency division, Dx, of the Divider 3.2. Dx = M+N+2.
Note) The M and N does not affect the duty of LVDS/CMOS output. The DCC(Duty Cycle
Correction) always works.
Bypasses (and power-down)3.2 divider logic, route input to 3.2 output.
0: do not bypass. (default)
1: bypass.
Bypasses (and power-down)3.1 divider logic, route input to 3.2 output.
0: do not bypass. (default)
1: bypass.
Nosync.
0: obey chip-level SYNC signal. (default)
1: ignore chip-level SYNC signal.
Forces divider 3 output to high. Requires that nosync also be set.
0: force low. (default)
1: force high.
Divider3.2 start high or start low.
0: start low. (default)
1: start high.
Divider3.1 strat high or start low.
0: start low. (default)
1: start high.
Sep-2012
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draft-E-02