AK8186B Datasheet, PDF (59/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Register
Address Bit(s)
(Hex)
Name
OUT7
141
0 _Power-Down
OUT8 Output
7:5 _Polarity
0x142
4 OUT8 CMOS B
OUT8 Select
3 LVDS/CMOS
OUT8 LVDS
2:1 Output
Current
OUT8
0 _Power-Down
OUT9 Output
7:5 _Polarity
0x143
4 OUT9 CMOS B
OUT9 Select
3 LVDS/CMOS
Description
Power-down output(LVDS/CMOS).
0: Power on.
1: Power off. (default) LVDS: Outputs Hi-Z CMOS: Outputs Low
In CMOS mode,[7:5] select the output polarity of each CMOS output.
In LVDS mode, only [5] determines LDVS polarity.
[7:6:5] OUT8(CMOS) OUT8n(CMOS) OUT8(LVDS)
0 0 0 Non-inverting. Inverting.
Non-inverting.
0 1 0 Non-inverting. Non-inverting.
Non-inverting (default)
1 0 0 Inverting.
Inverting.
Non-inverting
1 1 0 Inverting.
Non-inverting.
Non-inverting
0 0 1 Inverting.
Non-inverting.
Inverting
0 1 1 Inverting.
Inverting.
Inverting
1 0 1 Non-inverting. Non-inverting.
Inverting
1 1 1 Non-inverting. Inverting.
Inverting
In CMOS mode, turn on/off the OUT8n output. There is no effect in LDVS
mode.
0: turn off the OUT8n output. (default)
1: turn on the OUT8n output..
Selects LVDS or CMOS logic levels.
0: LVDS.
1: CMOS.
Sets output current level in LVDS mode. This has no effect CMOS mode,
[2:1] Current (mA) Recommend Termination (Ω)
0 0 1.75
100
0 1 3.5
100 (default)
1 0 5.25
50
1 1 7.0
50
Power-down output(LVDS/CMOS).
0: Power on.
1: Power off. (default) LVDS: Outputs Hi-Z CMOS: Outputs Low
In CMOS mode,[7:5] select the output polarity of each CMOS output.
In LVDS mode, only [5] determines LDVS polarity.
[7:6:5] OUT9(CMOS) OUT9n(CMOS) OUT9(LVDS)
0 0 0 Non-inverting. Inverting.
Non-inverting.
0 1 0 Non-inverting. Non-inverting.
Non-inverting (default)
1 0 0 Inverting.
Inverting.
Non-inverting
1 1 0 Inverting.
Non-inverting.
Non-inverting
0 0 1 Inverting.
Non-inverting.
Inverting
0 1 1 Inverting.
Inverting.
Inverting
1 0 1 Non-inverting. Non-inverting.
Inverting
1 1 1 Non-inverting. Inverting.
Inverting
In CMOS mode, turn on/off the OUT9n output. There is no effect in LDVS
mode.
0: turn off the OUT9n output. (default)
1: turn on the OUT9n output..
Selects LVDS or CMOS logic levels.
0: LVDS. (default)
1: CMOS.
draft-E-02
- 59 -
Sep-2012