AK8186B Datasheet, PDF (21/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
PLL
The AK8186B integrates a PLL with a VCO which can be configured to meet user’s application. The
following functions are set through a serial control port. The setting registers are mapped into 0x10 to 0x1F
in a register.
- PLL Power down
- Charge pump current
- R counter for Reference input
- A counter, B counter and Prescaler in loopback path
- Pin function of STATUS,LD and REFMON pins
- VCO calibration
- Lock Detect
- Frequency monitor of REF1, REF2 and VCO
- Switchover
- Holdover
Figure 10. PLL
REFERENCE INPUT
The reference input section of the AK8186B allows a differential input or two single-ended inputs. Both types
of inputs are self-biased. It allows easy ac-coupled input signals. The desired reference input is selected by
0x1C[2:0].
Single-ended input
A dc-coupled CMOS level signal or an ac-coupled sinewave or square wave signal can be input.
Differential input
An ac-coupled signal or a dc-coupled signal can be input. If a single-ended signal is applied to the
differential REFIN, the REFINn should be decoupled through a capacitor to a ground.
Note
All reference inputs are powered down by default.
When PLL is powered down, all the reference inputs are powered down.
When the differential mode is selected, the single-ended inputs are powered down and vice versa.
draft-E-02
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Sep-2012