AK8186B Datasheet, PDF (50/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Register
Address Bit(s)
(Hex)
Name
3 Disable DLD
0x018
VCO Cal
2:1 _Divider
0 VCO Cal Now
R,A,B
Counters
0x019 7:6 _{SYNC Pin}
RESET
0x01A
Reference
Frequency
6 _Monitor
Threshold
Description
Digital Lock Detect operation
0: normal lock detect operation (default)
1: disable lock detect
VCO Calibration Divider. Divider used to generate the VCO calibration clock
from the PLL reference clock.
[2:1] VCO Calibration Clock Divider
00 2
01 4
10 8
1 1 16 (default)
Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in
the active registers. The sequence to initiate a calibration is: program to 0,
followed by an update bit(Register 0x232[0]),; then programmed to 1, followed
by another update bit(Register 0x232[0]). This sequence gives complete
control over when the VCO calibration occurs relative to the programming of
other registers that can impact the calibration.
[7:6]
00
01
10
11
Action
Do nothing on SYNC(default)
Asynchronous reset
Synchronous reset
Do nothing on SYNC
Sets the reference (REF1/REF2) frequency monitor’s detection threshold
frequency. This does not affect the VCO frequency monitor’s detection
threshold. See Table 16: REF1, REF2 and VCO Frequency Status Monitor
parameter.
0: frequency valid if frequency is above the higher frequency threshold
(default).
1: frequency valid if frequency is above the lower frequency threshold.
Sep-2012
- 50 -
draft-E-02