AK8186B Datasheet, PDF (35/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

RESET
The AK8186B has three types of reset as below.
1) Power-on reset
2) Asynchronous reset by RESET pin
3) Soft Reset by 0x00[5]
AK8186B
Power-on reset (POR)
At power on, an internal power-on reset signal is generated which initializes the register to the default
settings. Note that the AK8186B does not execute the SYNC operation after power-on reset. To
synchronize the clock outputs by SYNC function after power-up, SYNC_B pin must be released more than
0.5μs after starting a VCO calibration.
VDD
POR Theshold
1.575V typ
3.135V
POR
____________
RESET pin
Register
Access
PLL Status
__________
SYNC pin
POR on
POR off
1μs ≤
Disable
Register access is effective 1 μs after the VDD rises over 3.135V.
Power Down
Enable
Update Registers
(0x232[0]=1)
Power On
Update Registers
Calibration
0.5μs ≤
__________
SYNC pin must be released more
than 0.5μs after a VCO calibration.
Figure 25. Recommended Power-up Sequence
Asynchronous reset by
pin
When the RESET pin is asserted, the AK8186B is immediately initialized to the default settings.
Soft reset by 0x00[5]
When the Soft reset bits 0x00[5] and [2] are set to 1, the AK8186B is immediately initialized to the default
settings except the Soft reset bits without setting the update register 0x232[0] to 1. Both soft reset bits must
be cleared by setting 0 since they are not self-cleaning bits.
draft-E-02
- 35 -
Sep-2012