AK8186B Datasheet, PDF (57/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

Register
Address Bit(s)
(Hex)
Name
4 Output Invert
0x0F3
OUT3 LVPECL
3:2 Differential
Voltage
OUT3
1:0 _Power-Down
4 Output Invert
0x0F4
OUT4 LVPECL
3:2 Differential
Voltage
OUT4
1:0 _Power-Down
4 Output Invert
0x0F5
OUT5 LVPECL
3:2 Differential
Voltage
OUT5
1:0 _Power-Down
Description
Selects output polarity.
0: non-inverting (default)
1: inverting
Sets the LVPECL output differential voltage(Vod)
[3:2] Vod(mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
LVPECL power-down modes.
[1:0] Out Mode
0 0 On Normal operation
0 1 Off Partial Power-down (Outputs Hi-Z).
1 0 Off Partial Power-down (Outputs Hi-Z). (default)
1 1 Off Power-down (Outputs Hi-Z).
Selects output polarity.
0: non-inverting (default)
1: inverting
Sets the LVPECL output differential voltage(Vod)
[3:2] Vod(mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
LVPECL power-down modes.
[1:0] Out Mode
0 0 On Normal operation (default)
0 1 Off Partial Power-down (Outputs Hi-Z).
1 0 Off Partial Power-down (Outputs Hi-Z).
1 1 Off Power-down (Outputs Hi-Z).
Selects output polarity.
0: non-inverting (default)
1: inverting
Sets the LVPECL output differential voltage(Vod)
[3:2] Vod(mV)
0 0 400
0 1 600
1 0 780 (default)
1 1 960
LVPECL power-down modes.
[1:0] Out Mode
0 0 On Normal operation
0 1 Off Partial Power-down (Outputs Hi-Z).
1 0 Off Partial Power-down (Outputs Hi-Z). (default)
1 1 Off Power-down (Outputs Hi-Z).
AK8186B
draft-E-02
- 57 -
Sep-2012