AK8186B Datasheet, PDF (61/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Register
Address Bit(s)
(Hex)
Name
0x194
0x196
Divider 1
4 _{Start High}
Divider 1
3:0 _{Phase Offset}
Divider 2
7:4 _{Low Cycles M}
Divider 2
3:0 _{High Cycles N}
Divider 2
7 _Bypass
Divider 2
6 Nosync
0x197
Divider 2
5 _{Force High}
Divider 2
4 _{Start High}
Divider 2
3:0 _{Phase Offset}
Description
Selects clock output to start high or start low.
0: start low. (default)
1: start high.
Phase offset. (default=0x0)
Number of Low clock cycles (M) and High clock cycles (N) of the divider input
define a frequency division, Dx, of the Divider 2. Dx = M+N+2.
Note) The M and N does not affect the duty of LVPECL output. The DCC(Duty Cycle
Correction) always works.
Bypasses and power-down the divider; route input to divider output.
0: use divider. (default)
1: bypass divider.
Nosync.
0: obey chip-level SYNC signal. (default)
1: ignore chip-level SYNC signal.
Forces divider output to high. This requires that nosync also be set.
0: divider output force to low. (default)
1: divider output force to high.
Selects clock output to start high or start low.
0: start low. (default)
1: start high.
Phase offset. (default=0x0)
draft-E-02
- 61 -
Sep-2012