AK8186B Datasheet, PDF (19/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

THEORY OF OPERATION
AK8186B
OPERATIONAL CONFIGURATIONS
The AK8186B can be configured in two ways below.
 Internal VCO and Clock Distribution
 External VCO and Clock Distribution
Each functional block must be set by the registers through a serial control port.
Internal VCO and Clock Distribution
When using the internal VCO and PLL, the things below are to be cared.
- Prescaler divide ratio : 8/9, 16/17 and 32/33 can be used to meet the maximum input frequency of A,B
counter, 300MHz.
- VCO calibration must be executed after the internal VCO is enabled.
Table 17 Settings for Internal VCO
Register
Function
0x10[1:0] = 00b
PLL normal operation (PLL on).
0x10 to 0x1E
PLL settings. Select and enable a reference input; set R,
N(P,A,B) PFD polarity, and Icp according to the intended loop
configuration.
0x18[0] = 0
Reset VCO calibration.
0x232[0] = 1
Register Update.
0x18[0] = 1
Initiate VCO calibration.
0x232[0] = 1
Register Update.
0x1E0[2:0]
Set VCO divider ratio.
0x1E1[0] = 0
Use the VCO divider as source for distribution section.
0x1E1[1] = 1
Select VCO as the source.
draft-E-02
Figure 8 Internal VCO and Clock Distribution
- 19 -
Sep-2012