AK8186B Datasheet, PDF (23/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
PHASE FREQUENCY DETECTOR (PFD)
The PFD has two inputs of R divider and N divider. It outputs an up/down signal for the charge pump, which
is proportional to the phase and frequency difference between the inputs. Both input frequencies must not
exceed the maximum frequency of 100MHz.
CHARGE PUMP (CP)
The charge pump pumps up/down controlled by the output of the PFD. The output current of the CP goes
out through the CP pin and integrated and filtered by the external loop filter, then is finally turned into a
voltage. The voltage goes into the VCO via the LF pin to tune the VCO frequency.
The CP has four modes of operation and eight current values. Each of them can be set by the registers
below.
Table 19 Register for Charge Pump Operation Mode
Item
Register
Description
Operation Mode
0x10[3:2]
Normal, High Impedance, Pump up, Pump down
CP Current
0x10[6:4]
0.6 to 4.8 mA with 0.6mA step (CPRSET=5.1kΩ)
On-Chip VCO
The AK8186B integrates a VCO working in the range of 1.75GHz to 2.25GHz. The VCO requires a
calibration to achieve optimal operation around the REFIN frequency. After power-up or reset. a initial
calibration is required along with the procedure shown below. The calibration can be executed at anytime
after power-up or reset from the step marked (*). SYNC function is executed during the VCO calibration.
Distribution outputs remain static in this period. Maximum time of the VCO calibration is 4400 cycles of a
VCO calibration clock supplied by a VCO calibration divider. The VCO calibration divider divides the R
divider output (= the PFD input clock) with the divider value of 2,4,8 or 16 set to 0x18[2:1]. When the
calibration is finished, a logic true (1b) is returned to a readback bit 0x1F[6].
After power-up or reset.
Set the PLL registers to the proper values for
the PLL loop.
(*)
Initiate VCO calibration
0x18<0>=0
0x232<0>=1 (Update registers)
0x18<0>=1
0x232<0>=1 (Update registers)
VCO calibration starts.
A SYNC function starts.
Outputs goes into static state.
Sets the PLL to proper values.
VCO calibration finishes.
Internal SYNC signal is released.
The outputs start clocking.
The PLL locks.
Figure 11. Procedure of VCO calibration
draft-E-02
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Sep-2012