AK8186B Datasheet, PDF (13/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

Parameter
CLK-TO-CMOS Additive Phase Noise
CLK=500MHz, Output=250MHz,
Divider=2
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
CLK=500MHz, Output=50MHz,
Divider=10
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
AK8186B
Min
Typ
Max
Unit
Test Conditions/Comments
Dose not include PLL and VCO
Input slew rate > 1 V/ns
-113
-135
-143
-149
-152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
-129
-139
-149
-156
-160
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Clock Output Phase Noise (Internal VCO Used)
Table 9. All specifications at VDD=3.3V5%, VDD_LVPECL= 2.375V to VDD, Ta: -40 to +85℃, unless otherwise noted
Parameter
LVPECL Phase Noise
Fvco=2.24256GHz, Fout=280.32MHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
Fvco=1.96608GHz, Fout=245.76MHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
Fvco=1.75104GHz, Fout=218.88MHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
Min
Typ
Max
Unit
Test Conditions/Comments
through VCO divider and channel divider
-94
-103
-105
-125
-135
-136
dBc/Hz ^{REF=122.88MHz}
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-89
-102
-106
-127
-136
-137
dBc/Hz ^{REF=122.88MHz}
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-96
-105
-108
-129
-137
-138
dBc/Hz ^{REF=122.88MHz}
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
draft-E-02
- 13 -
Sep-2012