AK8186B Datasheet, PDF (31/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
CLOCK DISTRIBUTION
VCO DIVIDER
The VCO divider provides frequency division between the internal VCO and the clock distribution section.
The VCO divider can be set to divide by 2,3,4,5 and 6 (0x1E0[2:0]). The output of the VCO divider has 50%
duty even though the division is 3 and 5 due to the duty cycle compensation circuit. VCO divider can be
_______________
bypassed when using an external VCO/VCXO. When bypassed, the input duty through CLK/CLK pins is not
compensated.
Channel Dividers for LVPECL OUTPUTS
There are three channel dividers for LVPECL outputs. Each divider drives a pair of LVPECL outputs. The
divider value Dx can be set 1 to 32.
Dx : M + N +2 (M,N : 0 to 15, Dx = 1 when the bypass bit is set.)
Table 25 Registers for LVPECL Channel Divider 0,1 and 2
Channel
Low Cycles
High Cycles
Divider
M
N
0
0x190[7:4]
0x190[3:0]
1
0x193[7:4]
0x193[3:0]
2
0x196[7:4]
0x196[3:0]
Bypass
0x191[7]
0x194[7]
0x197[7]
LVPECL outputs
OUT0, OUT1
OUT2, OUT3
OUT4, OUT5
The divider has the duty cycle correction. It always operates and outputs 50% duty clocks.
Channel Dividers for LVDS/CMOS OUTPUTS
There are two channel dividers for LVDS/CMOS outputs. Each divider drives a pair of LVDS outputs(or two
pair of CMOS outputs). The divider value Dx can be set 1 to 32.
Dx : M + N +2 (M,N : 0 to 15, Dx = 1 when the bypass bit is set.)
Table 26 Registers for LVPECL Channel Divider 3 and 4
Channel
Low Cycles
High Cycles
Divider
M
N
3 3.1
0x199[7:4]
0x199[3:0]
3.2
0x19B[7:4]
0x19B[3:0]
4 4.1
0x19E[7:4]
0x19E[3:0]
4.2
0x1A0[7:4]
0x1A0[3:0]
Bypass
0x19C[4]
0x19C[5]
0x1A1[4]
0x1A1[5]
LVDS/LVCMOS outputs
OUT6(A,B), OUT7(A,B)
OUT8(A,B), OUT9(A,B)
The divider has the duty cycle correction. It always operates and outputs 50% duty clocks.
draft-E-02
- 31 -
Sep-2012