AK8186B Datasheet, PDF (34/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
LVPECL OUTPUTS : OUT0 to OUT5
The AK8186B has three pair of LVPECL buffers. Each pair has dedicated VDD supply pin, VDD_LVPECL,
allowing for a separate power supply to be used. VDD_LVPECL can be from 2.5V to 3.3V.
Table 29 LVPECL OUTPUTS Control Register
Control Item
Register
Invert Polarity
0xF0 to F5 [4]
Differential Voltage
0xF0 to F5 [3:2]
Power down*
0xF0 to F5 [1:0]
*)LVPECL outputs Hi-Z.
There are two modes of power down.
- Partial power down
- Power down
In Partial power down, an output stage is off but
a differential input stage is on.
Output Stage
Differential Input Stage
Figure 23. LVPECL Equivalent Circuit
LVDS/CMOS OUTPUTS : OUT6 to OUT9
OUT6 to OUT9 can be configured as an LVDS output or a pair of CMOS outputs.
Table 30 LVDS/CMOS outputs control register
Control Item
Register
Output Polarity
0x140 to 143 [7:5]
CMOS B turn on/off 0x140 to 143 [4]
Select LVDS/CMOS 0x140 to 143 [3]
LVDS Output Current 0x140 to 143 [2:1]
Power down*
0x140 to 143 [0]
*)LVDS outputs Hi-Z. CMOS outputs Low.
Figure 24. LVDS/CMOS Equivalent Circuit
Sep-2012
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draft-E-02