AK8186B Datasheet, PDF (33/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
When the Start High bit =1, the default phase offset exists before the phase offset defined by the phase
offset bits. The default phase offset varies depending on the divider ratio. When the divider is bypassed, the
Default Offset is equal to zero.
Total Phase Offset = Default Phase Offset + Phase Offset bits
Default Phase Offset
Start High bit = 0 : Zero
Start High bit = 1 : Roundup(Divider Ratio/2)
where Divider Ratio >=2
Example;
Divider ratio = 3, Phase Offset bits = 2, then Default phase offset = 2
Total Phase Offset = 2 + 2 = 4 clock cycles
Figure 21, 22 shows how those offsets work.
Input to
VCO Divider
Input to
Channel Divider
SYNCb PIN
Output of Channel Divider
Start High = 0
Divide Ratio = 2
Phase Offset = 0
Start High = 0
Divide Ratio = 2
Phase Offset = 1
Start High = 0
Divide Ratio = 2
Phase Offset = 2
Start High = 0
Divide Ratio = 3
Phase Offset = 0
Start High = 0
Divide Ratio = 3
Phase Offset = 1
1 2 14 15
Start Low
Phase Offset = 1
Phase Offset = 2
Phase Offset = 1
Total Phase Offset
= Default Phase Offset + Phase Offset (by register bits)
Total Phase Offset = 0 + 0 = 0
Total Phase Offset = 0 + 1 = 1
Total Phase Offset = 0 + 2 = 2
Total Phase Offset = 0 + 0 = 0
Total Phase Offset = 0 + 1 = 1
Figure 21. Channel Divider Phase Offset with Start High bit = 0 (Start Low)
Input to
VCO Divider
Input to
Channel Divider
SYNCb PIN
Output of Channel Divider
Start High = 1
Divide Ratio = 2
Phase Offset = 0
Start High = 1
Divide Ratio = 2
Phase Offset = 1
Start High = 1
Divide Ratio = 2
Phase Offset = 2
Start High = 1
Divide Ratio = 3
Phase Offset = 0
Start High = 1
Divide Ratio = 3
Phase Offset = 1
1 2 14 15
Start High ^{Default Phase Offset = 1}
Phase Offset = 1
Phase Offset = 2
Default Phase Offset = 2
Phase Offset = 1
Total Phase Offset
= Default Phase Offset + Phase Offset (by register bits)
Total Phase Offset = 1 + 0 = 1
Total Phase Offset = 1 + 1 = 2
Total Phase Offset = 1 + 2 = 3
Total Phase Offset = 2 + 0 = 2
Total Phase Offset = 2 + 1 = 3
Figure 22 Channel Divider Phase Offset with Start High bit = 1 (Start High)
draft-E-02
- 33 -
Sep-2012