AK8186B Datasheet, PDF (22/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
The maximum input frequency of both type of inputs is 250MHz.
REFERENCE SWITCHOVER
When dual single-ended CMOS inputs are imposed to REF1 and REF2, the AK8186B could support
automatic and manual PLL reference clock switching between REF1 and REF2. The automatic switchover
is enabled by setting 0x1C[4].
0x1C[4] = 0 : manual switchover
1 : automatic switchover
Note;
The single-ended inputs should be dc-coupled CMOS levels and not go to high impedance. If these go to
high impedance, input buffers may cause chattering due to noise. A false detection might occur.
Manual Switchover
A PLL reference input can be selected by a register or a pin.
0x1C[5] assigns the register 0x1C[6] or the REF_SEL pin to select a PLL reference input.
Automatic Switchover
Automatic switchover has two modes of operation. Both of them switch from REF1 to REF2 when REF1 is
lost. The difference of the two modes is whether the AK8186B would stay on REF2 or not when REF1
returns. 0x1C[3] selects one of the two modes.
0x1D[3] = 0 : Switch to REF1.
1 : Stay on REF2. It can be switched to REF1 manually.
Condition to switch from REF1 to REF2
If the reference switchover circuit detects three consecutive rising edges of REF2 without any REF1 rising
edges, the REF1 is considered to be lost. On the 2nd subsequent rising edge of REF2, the reference clock
input to PLL is switched from REF1 to REF2.
Condition to switch back to REF1 when 0x1D[3]=0
If the reference switchover circuit detects four consecutive rising edges of REF1 without three consecutive
REF2 rising edges between REF1 edges, the REF1 is considered to be returned. On the 2nd subsequent
rising edge of REF2, the reference clock input to PLL is switched from REF2 to REF1.
R DIVIDER (REFERENCE DIVIDER)
The reference input goes into the R divider ( a 14-bit counter). It can be set to any value from 0 to 16383 by
0x11 and 0x12. When 0 is set, the input is divided by 1.
Maximum output frequency
The output of the R divider goes to one of the PFD inputs which is compared to the output of the N divider.
The frequency applied to the PFD must not exceed 100MHz.
Reset
The R is divider can be reset under the following conditions.
1) Power on reset
2) When RESET is asserted low.
3) When 0x16[6] is set to 1 (reset of the R divider)
4) When 0x16[5] is set to 1 (shared reset bit of the R, A and B counter)
5) When SYNC is released from L to H.
Sep-2012
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draft-E-02