AK8186B Datasheet, PDF (32/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Synchronizing the Outputs: SYNC FUNCTION
The AK8186B clock outputs can be synchronized to each other. The SYNC function starts to operate by the
following conditions.
1) The SYNCpin is forced low and then released (Manual sync).
2) By setting and then resetting the soft sync bit 0x230[0]
3) After a VCO calibration is completed.
The channel divider output status depends on the register setting of the channel divider such as Bypass bit,
NoSync bit, Force High bit, Start High bit and Phase offset bits.
Input to
VCO Divider
Input to
Channel Divider
SYNCb PIN
Output of
Channel Divider
Output of
Channel Divider
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Start Low
Start High
14 or 15 cycles at channel divider
Figure 20. SYNC timing
Sync function can be disabled by NOSYNC bit. When the NOSYNC bit is set to 1, the SYNC function is
disabled.
Table 27 SYNC Disable on Channel Divider
Channel
NOSYNC bit
Divider
0
0x191[6]
1
0x194[6]
2
0x197[6]
3.1, 3.2
0x19C[3]
4.1, 4.2
0x1A1[3]
Phase Offset
Each channel divider has a programmable phase offset function. Phase offset means a delay to rising edge
of output clock from zero offset output. Two kinds of bits such as Start High bit and Phase Offset bits affect
Total Phase Offset. The phase offset is effective when the SYNC function is invoked.
Table 28 Start High and Phase Offset Registers on Channel Divider
Channel
Start High
Phase Offset
Divider
0
0x191[4]
0x191[3:0]
1
0x194[4]
0x194[3:0]
2
0x197[4]
0x197[3:0]
3.1
0x19C[0]
0x19A[3:0]
3.2
0x19C[1]
0x19A[7:4]
4.1
0x1A1[0]
0x19F[3:0]
4.2
0x1A1[1]
0x19F[7:4]
Sep-2012
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draft-E-02