AK8186B Datasheet, PDF (65/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
System
Register
Address Bit(s)
(Hex)
Name
Power-Down
2 _SYNC
Description
Powers down the SYNC function.
0: normal operation of SYNC function (default).
1: Power-down SYNC circuitry.
0x230
Powers down the output buffers.
0 : normal operation (default).
Power down 1 : power down the output buffers.
1 distribution
Buffers output as follows in power down.
reference
LVPECL: Hi-Z (same state with 0xFn[1:0]=01 or 10b, n=0 to 5)
LVDS: Hi-Z
CMOS: Low
0 Soft SYNC
The soft SYNC works the same as the SYNC pin. Expect that the polarity of
the bit is reversed. That is, a high level forces selected channels into a
predetermined static state, and 1-to-0 transition triggers a SYNC.
0: same as SYNC high (default).
1: same as SYNC low.
Update All Registers
Register
Address Bit(s)
(Hex)
Name
0x232
Update All
0 _Registers
Description
This bit must be set to 1 to transfer the contents of the buffer registers into the
active registers. This happens on the next SCLK rising edge. This bit is
self-cleaning; that is, it does not have to be set back to 0.
1: (self-cleaning); update all active registers to the contents of the buffer
registers.
draft-E-02
- 65 -
Sep-2012