AK8186B Datasheet, PDF(3/69 Page) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

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AK8186B Datasheet, PDF (3/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

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TABLE OF CONTENTS

FEATURES.....................................................................- 1 -

DESCRIPTION................................................................- 1 -

ORDERING INFORMATION............................................- 1 -

BLOCK DIAGRAM..........................................................- 2 -

PIN DESCRIPTION .........................................................- 4 -

PIN CONFIGURATION................................................... - 4 -

PIN FUNCTION ............................................................. - 5 -

ABSOLUTE MAXIMUM RATING.....................................- 7 -

RECOMMENDED OPERATING CONDITIONS...................- 7 -

ELECTRICAL CHARACTERISTICS......................................- 7 -

POWER DISSIPATION ......................................................... - 7 -

PLL CHARACTERISTICS ....................................................... - 8 -

CLOCK INPUT CHARACTERISTICS ........................................... - 9 -

CLOCK OUTPUT CHARACTERISTICS ...................................... - 10 -

TIMING CHARACTERISTICS................................................. - 11 -

CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO

DIVIDER NOT USED)........................................................- 12 -

CLOCK OUTPUT PHASE NOISE (INTERNAL VCO USED) ............ - 13 -

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING

INTERNAL VCO) ............................................................. - 14 -

CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING

EXTERNAL VCXO) .......................................................... - 14 -

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) .. -

15 -

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) ... - 15 -

SERIAL CONTROL PORT .................................................... - 16 -

AND

................................................. - 17 -

LD, STATUS AND REFMON ........................................... - 17 -

TIMING DIAGRAMS....................................................- 18 -

THEORY OF OPERATION .............................................- 19 -

OPERATIONAL CONFIGURATIONS ............................. - 19 -

Internal VCO and Clock Distribution .................... - 19 -

External VCO and Clock Distribution.................... - 20 -

PLL ............................................................................. - 21 -

REFERENCE INPUT ............................................... - 21 -

REFERENCE SWITCHOVER.................................... - 22 -

R DIVIDER (REFERENCE DIVIDER)......................... - 22 -

PHASE FREQUENCY DETECTOR (PFD) .................. - 23 -

CHARGE PUMP (CP) ............................................. - 23 -

On-Chip VCO ........................................................ - 23 -

External VCO/VCXO ............................................. - 24 -

PLL EXTERNAL LOOP FILTER................................. - 24 -

Figure 12 Example of External Loop Filter for the

Internal VCO

Figure 13 Example of External

AK8186B

Loop Filter for an External VCO............................ - 24 -

FEEDBACK DIVIDER (N DIVIDER) .......................... - 24 -

LOCK DETECT ....................................................... - 26 -

HOLDOVER........................................................... - 28 -

Frequency Status Monitors .................................. - 30 -

CLOCK DISTRIBUTION ................................................- 31 -

VCO DIVIDER........................................................ - 31 -

Channel Dividers for LVPECL OUTPUTS ................ - 31 -

Channel Dividers for LVDS/CMOS OUTPUTS ........ - 31 -

Synchronizing the Outputs: SYNC FUNCTION....... - 32 -

Phase Offset......................................................... - 32 -

LVPECL OUTPUTS : OUT0 to OUT5 ....................... - 34 -

LVDS/CMOS OUTPUTS : OUT6 to OUT9 ............... - 34 -

RESET.........................................................................- 35 -

Power-on reset (POR) .......................................... - 35 -

Asynchronous reset by

pin ...................... - 35 -

Soft reset by 0x00[5] ............................................ - 35 -

POWER DOWN MODES..............................................- 36 -

Chip Power Down by PDn pin............................... - 36 -

PLL Power Down .................................................. - 36 -

REF1, REF2 Power Down ...................................... - 36 -

VCO and CLK Input Power Down.......................... - 36 -

Distribution Power Down..................................... - 36 -

Individual Clock Output Power Down (OUT0 to OUT9)-

37 -

SERIAL CONTROL PORT ..............................................- 38 -

SERIAL CONTROL PORT PIN DESCRIPTIONS ......... - 38 -

GENERAL DESCRIPTION OF SERIAL CONTROL PORT- 38

Communication Cycle .......................................... - 38 -

The Instruction Word (16 bits) ............................. - 39 -

WRITE .................................................................. - 39 -

READ .................................................................... - 40 -

BUS STALLING IN READ/WRITE ACCESS ............... - 40 -

MSB/LSB FIRST TRANSFERS.................................. - 41 -

Serial Port Configuration ..................................... - 46 -

PLL Configuration................................................. - 47 -

LVPECL Outputs ................................................... - 56 -

LVDS/CMOS Outputs............................................ - 58 -

LVPECL Channel Dividers...................................... - 60 -

LVDS/CMOS Channel Dividers.............................. - 62 -

VCO Divider and CLK Input................................... - 64 -

System ................................................................. - 65 -

Update All Registers ............................................ - 65 -

PACKAGE INFORMATION ........................................... - 66 -

MECHANICAL DATA .........................................................- 66 -

MARKING .....................................................................- 66 -

draft-E-02

Sep-2012

-3-

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