AK8186B Datasheet, PDF (40/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
SCLK
CS
SDO
SDIO
Serial
Control
Port
Update
Registers
Update register operation is executed
when set 0x232<0>=1.
Figure 30. Buffer/Active Register
The serial control port configuration registers of 0x00 and 0x04 does not require the update register. The
written data is immediately effective.
READ
When I15=1, read operation is executed. The timing chart of 3-byte data read is shown below. Read data is
valid at the falling edge of SCLK.
Figure 31. Serial Control Port - READ - MSB First
The serial control port can read back the data in the buffer registers or in the active registers. 0x04[0] selects
which register is read.
SCLK
CS
SDO
SDIO
Serial
Control
Port
Readback of the buffer registers or the active registers
Figure 32. Readback Registers
Read in Streaming mode
When data is transferred in streaming mode, the reserved and blank registers are not skipped over.
Bidirectional/Unidirectional mode
By default, the serial control port operates in the bidirectional mode. Both write data and readback data are
transferred on the SDIO pin. In unidirectional mode, the readback data is on the SDO pin. 0x00[7][0]
enables the SDO pin.
BUS STALLING IN READ/WRITE ACCESS
Sep-2012
- 40 -
draft-E-02