AK8186B Datasheet, PDF (63/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Register
Address
(Hex)
0x19E
Bit(s)
Name
Divider 4.1
7:4 _{Low Cycles M}
Divider 4.1
3:0 _{High Cycles N}
0x19F
Divider 4.2
7:4 _{Phase Offset}
Divider 4.1
3:0 _{Phase Offset}
0x1A0
Divider 4.2
7:4 _{Low Cycles}
Divider 4.2
3:0 _{High Cycles}
Divider 4.2
5 _Bypass
Divider 4.1
4 _Bypass
0x1A1
Divider 4
3 _Nosync
Divider 4
2 _{Force High}
Divider 4.2
1 _{Start High}
Divider 4.1
0 _{Start High}
Description
Number of Low clock cycles (M) and High clock cycles (N) of the divider input
define a frequency division, Dx, of the Divider 4.1. Dx = M+N+2.
Note) The M and N does not affect the duty of LVDS/CMOS output. The DCC(Duty Cycle
Correction) always works.
Refer to LVDS/CMOS channel divider function description.
Refer to LVDS/CMOS channel divider function description.
Number of Low clock cycles (M) and High clock cycles (N) of the divider input
define a frequency division, Dx, of the Divider 4.2. Dx = M+N+2.
Note) The M and N does not affect the duty of LVDS/CMOS output. The DCC(Duty Cycle
Correction) always works.
Bypasses (and power-down)4.2 divider logic, route input to 4.2 output.
0: do not bypass. (default)
1: bypass.
Bypasses (and power-down)4.1 divider logic, route input to 4.2 output.
0: do not bypass. (default)
1: bypass.
Nosync.
0: obey chip-level SYNC signal. (default)
1: ignore chip-level SYNC signal.
Forces divider 4 output to high. Requires that nosync also be set.
0: force low. (default)
1: force high.
Divider4.2 start high or start low.
0: start low. (default)
1: start high.
Divider4.1 strat high or start low.
0: start low. (default)
1: start high.
draft-E-02
- 63 -
Sep-2012