AK8186B Datasheet, PDF (54/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Register
Address
(Hex)
Bit(s)
Name
PLL Status
4 Register
Disable
LD Pin
3 Comparator
Enable
0x01D
Holdover
2 _Enable
Manual
1 Holdover
Control
Holdover
0 _Enable
Description
Disable the PLL status register read-back.
0: enable (default)
1: disable
Enable the LD pin voltage comparator, This function is used with the LP pin
current source lock detect mode. When in the automatic holdover mode, this
enables the use of the voltage on the LD pin to determine if the PLL was
previously in a locked state. Otherwise, this can be used with the REFMON and
STATUS pins to monitor the voltage on this PIN.
0: disable (default)
1: enable
Along with[0] enables the holdover function.
0: holdover disabled (default)
1: holdover enabled
Enable the manual hold control through the SYNC pin. (This disables the
automatic holdover mode.)
0: automatic holdover mode-holdover controlled by automatic holdover
circuit. (default)
1: manual holdover mode-holdover controlled by SYNC pin.
Analog with[2] enables the holdover function.
0: holdover disabled (default)
1: holdover enabled
Sep-2012
- 54 -
draft-E-02