AK8186B Datasheet, PDF (27/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
(0x1B[4:0]). Selecting a properly value of capacitor allows a lock detect indication to be delayed. The LD pin
comparator trip point is shown in Table 16.
AK8186B
110µA
DLD
300Ω
LD
LD PIN
C
COMPARATOR
REFMON or
STATUS
Figure 16. Current Source Lock Detect
Analog Lock Detect (ALD)
When 0x1A[5:0] is set to the value shown below, the Analog Lock Detect is indicated at the LD pin. The ALD
function requires a external R-C filter to indicate lock/unlock state.
0x1A[5:0] = 01h : P-channel open drain ALD (Active Low)
0x1A[5:0] = 02h : N-channel open drain ALD (Active High)
AK8186B
ALD
VDD=3.3V
LD ^R1
R2
V_OUT
C
ALD
AK8186B
LD ^R1
R2
V_OUT
C
Figure 17. Analog Lock Detect (N/P-channel open drain)
N-channel open drain
The ALD signal is derived from the up/down control outputs of the PFD.
 When the PLL is in lock, the ALD signal is mainly low with minimum high-going pulse. This leads the
voltage of LD to getting up to VDD.
 When the PLL in in unlock, the ALD signal has a wider high-going pulse. This leads the voltage of LD to
getting down to ground.
P-channel open drain
The ALD signal is the inverting of the ALD.
 When the PLL is in lock, the ALD signal is mainly high with minimum low-going pulse. This leads the
voltage of LD to getting down to ground.
 When the PLL in in unlock, the ALD signal has a wider high-going pulse. This leads the voltage of LD
getting up to VDD.
draft-E-02
- 27 -
Sep-2012