AK8186B Datasheet, PDF (20/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
External VCO and Clock Distribution
When using the external VCO and PLL, the things below are to be cared.
- Prescaler divide ratio : 1, 2/3, 4/5, 8/9, 16/17 and 32/33 can be used to meet the maximum input
frequency of A,B counter, 300MHz.
- Maximum frequency of the External VCXO is 500MHz.
Table 18 Settings for External VCO
Register
Function
0x10[1:0] = 00b
PLL normal operation (PLL on).
0x10[7] = 0 or 1
PFD polarity 0: positive 1:negative
0x10 to 0x1E
PLL settings. Select and enable a reference input; set R,
N(P,A,B) PFD polarity, and Icp according to the intended loop
configuration.
0x1E0[2:0]
Set VCO divider ratio.
0x1E1[0] = 0 or 1
Select the source for distribution section.
0: VCO divider 1: CLK input
0x1E1[1] = 0
Select the CLK input as the source.
Figure 9 External VCO and Clock Distribution
Sep-2012
- 20 -
draft-E-02