AK8186B Datasheet, PDF (41/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
When 1, 2 or 3-byte transfer, but not streaming, CS can rise up on boundary of every data byte to stall the
bus. While CS is high, read/write operation is suspended and the state machine of the serial control port
stays in wait state. The operation resumes after CS goes down.
Figure 33. Bus Stalling
If the system gets out of the wait state, the state machine should be reset by the following procedure.
Return CS low and complete the transfer of remained data.
Return CS low for at least one complete SCLK cycle (but less than 8 cycles).
If CS goes high on non-boundary area, the read/write access is immediately cancelled.
MSB/LSB FIRST TRANSFERS
The AK8186B serial control port transfer the data by MSB first or LSB first. 0x00[6][1] selects one of which.
Default is MSB first.
MSB first
The instruction and data are transferred from MSB. When the AK8186B executes multibyte access, the
address included in the instruction is the start address. Address decrements at every data byte access.
Figure 34. MSB First Transfers
draft-E-02
- 41 -
Sep-2012