AK8186B Datasheet, PDF (48/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Register
Address Bit(s)
(Hex)
Name
Reset A&B
5 _Counters
Reset All
4 _Counters
B Counter
3 _Bypass
0x016
Prescaler P
2:0
STATUS
0x017 7:2 _{Pin Control}
Description
Resets A&B counters (part of N divider)
0: normal (default)
1: reset A & B counter.
Resets R, A&B counters.
0: normal (default)
1: reset R, A & B counter.
B counter bypass. This is valid only when operating the prescaler in FD mode.
0: normal mode (default)
1: B counter is set to divide-by-1. This allows the prescaler setting to
determine the divide for the N divider.
Prescaler: DM=Dual modulus and FD = fixed divide.
External VCO/VCXO ; 1E1[1]=0
[2:1:0] Mode Prescaler
0 0 0 FD Divide-by-1
0 0 1 FD Divide-by-2
0 1 0 DM Divide-by-2 (2/3 mode)
0 1 1 DM Divide-by-4 (4/5 mode)
1 0 0 DM Divide-by-8 (8/9 mode)
1 0 1 DM Divide-by-16 (16/17 mode)
1 1 0 DM Divide-by-32 (32/33 mode) (default)
1 1 1 FD Divide-by-3
Internal VCO ; 1E1[1]=1
[2:1:0] Mode Prescaler
0 X X DM Divide-by-32 (32/33 mode)
1 0 0 DM Divide-by-8 (8/9 mode)
1 0 1 DM Divide-by-16 (16/17 mode)
1 1 X DM Divide-by-32 (32/33 mode)
Selects the signal that is connected to the STATUS pin.
Level or
Dynamic
[7:6:5:4:3:2] Signals Signal at STATUS Pin
0 0 0 0 0 0 LVL
Ground(dc) (default).
0 0 0 0 0 1 DYN
N divider output
0 0 0 0 1 0 DYN
R divider output
0 0 0 0 1 1 DYN
A divider output.
0 0 0 1 0 0 DYN
Prescaler output.
0 0 0 1 0 1 DYN
PFD up pulse
0 0 0 1 1 0 DYN
PFD down pulse
0 x x x x x LVL
Ground(dc);for all other cases 0xxxxx not specified
Above.
The selections that follow are the same as REFMON.
1 0 0 0 0 0 LVL
Ground(dc).
1 0 0 0 0 1 DYN
REF1 clock
1 0 0 0 1 0 DYN
REF2 clock (N/A differential mode)
1 0 0 0 1 1 DYN
Selected reference to PLL
1 0 0 1 0 0 DYN
Unselected reference to PLL
1 0 0 1 0 1 LVL
Status of selected reference
1 0 0 1 1 0 LVL
Status of unselected reference
1 0 0 1 1 1 LVL
Status REF1 frequency.(active high)
Sep-2012
- 48 -
draft-E-02