AK8186B Datasheet, PDF (44/69 Pages) Asahi Kasei Microsystems – Multi Output Clock Generator with Integrated 2.0GHz VCO

AK8186B
Addr
(HEX)
A0
Parameter
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC to
EF
LVPECL Outputs
F0 OUT0
F1 OUT2
F2 OUT2
F3 OUT3
F4 OUT4
F5 OUT5
F6-13
F
LVDS/CMOS Outputs
140 OUT6
Bit 7
Bit 6
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
Blank
OUT6 CMOS Output
Polarity
141 OUT7
OUT7 CMOS Output
Polarity
142 OUT8
OUT8 CMOS Output
Polarity
143 OUT6
OUT9 CMOS Output
Polarity
144-1
8F
LVPECL Channel Dividers
Bit 5
Bit 4
Blank
Blank
Blank
Blank
Bit 3
Bit 2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Blank
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Default
Value
01
00
00
01
00
00
01
00
00
01
00
00
OUT0
Invert
OUT1
Invert
OUT2
Invert
OUT3
Invert
OUT4
Invert
OUT5
Invert
OUT0 LVPECL
Differential Voltage
OUT1 LVPECL
Differential Voltage
OUT2 LVPECL
Differential Voltage
OUT3 LVPECL
Differential Voltage
OUT4 LVPECL
Differential Voltage
OUT5 LVPECL
Differential Voltage
Blank
OUT0 Power-Down
08
OUT1 Power-Down
0A
OUT2 Power-Down
08
OUT3 Power-Down
0A
OUT4 Power-Down
08
OUT5 Power-Down
0A
OUT6
LVDS/CMOS
Output
Polarity
OUT7
LVDS/CMOS
Output
Polarity
OUT8
LVDS/CMOS
Output
Polarity
OUT9
LVDS/CMOS
Output
Polarity
OUT6
CMOS B
OUT7
CMOS B
OUT8
CMOS B
OUT9
CMOS B
OUT6 Select
LVDS/CMOS
OUT7 Select
LVDS/CMOS
OUT8 Select
LVDS/CMOS
OUT9 Select
LVDS/CMOS
Blank
OUT6 LVDS Output
Current
OUT7 LVDS Output
Current
OUT8 LVDS Output
Current
OUT9 LVDS Output
Current
OUT6
Power-Down
42
OUT7
Power-Down
43
OUT8
Power-Down
42
OUT9
Power-Down
43
190
191
Divider 0
(PECL)
192
Divider 0 Low Cycles
Divider 0
Bypass
Divider 0
No Sync
Divider 0
Force High
Blank
Divider 0
Start High
Reserved
Divider 0 High Cycles
00
Divider 0 Phase Offset
80
Reserved
00
193
194
Divider 1
(PECL)
195
Divider 1 Low Cycles
Divider 1
Bypass
Divider 1
No Sync
Divider 1
Force High
Blank
Divider 1
Start High
Reserved
Divider 1 High Cycles
BB
Divider 1 Phase Offset
00
Reserved
00
196
197
Divider 2
(PECL)
198
Divider 2 Low Cycles
Divider 2
Bypass
Divider 2
No Sync
Divider 2
Force High
Blank
Divider 2
Start High
Reserved
Divider 2 High Cycles
00
Divider 2 Phase Offset
00
Reserved
00
Sep-2012
- 44 -
draft-E-02